The present invention relates in general to semiconductor technology, and more particularly, to structures and methods for reducing dopant out-diffusion from implant regions, such as source and heavy body regions, in power field effect transistors (FETs).
In the design of FETs it is desirable to have a heavily doped body region that extends below the source region. This heavy body region provides a low resistance path around the source area to keep the well-source junction from becoming forward biased, thus preventing a parasitic bipolar transistor inherently present in power FETs from turning on. The ability of the transistor to avoid turning on this parasitic bipolar transistor is commonly referred to as ruggedness. A deep heavy body region also helps move the electric field and its breakdown current path away from the gate dielectric. Moving the electric field away from the gate dielectric reduces the possibility of damage by hot electrons.
Some technologies improve transistor ruggedness and gate dielectric integrity by forming a heavy body region using a high energy implant followed by a temperature cycle to drive the heavy body dopants to the desired depth. The temperature cycle that drives in the dopants, however, as well as other temperature cycles during the manufacturing process, cause lateral diffusion of the heavy body and source dopants. Laterally diffused heavy body and/or source dopants may interfere with the active channel area and alter transistor threshold voltage. Also, laterally diffused source dopants may increase the heavy body contact resistance. To avoid these effects, limits are placed on minimum cell pitch. However, a larger cell pitch reduces device density and increases drain-to-source on resistance (RDSon), which adversely affects transistor performance.
Thus, there is a need for structures and methods for reducing dopant out-diffusion from heavy body and source regions in power FETs.